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Re: [sc-users] Problem in Demand/Dwhite?
That's what I was missing, then. Good to know!
That leaves the case where the first impulse is delayed (due to non-zero phase, or Dust being the trigger).
One could initialize using the result of a "preparatory" trigger, but the user might reasonably complain that that's not what they asked for, and in some cases would lead to outright bugs if not special-cased (e.g. Dseq, where the user's first trigger would return the second element).
Despite the drawback of initializing to zero being "surprising" in the case where it's outside the possible trigger response of the Demand, and having the potential to have bad things happen downstream (as in the reciprocal case), it seems a lot easier to define and explain. A line in the Demand documentation saying something like "the Demand Ugen will output zero until it receives its first trigger" would do the trick.
> On Dec 6, 2019, at 6:36 PM, jamshark70@xxxxxxxxx wrote:
>
> On Fri, Dec 6, 2019 at 10:49 AM <walters@xxxxxxxxxxxxxxxxxx> wrote:
>> Following up, though, I think that in this example the initial value issue is in Demand, not Impulse. That's what .reciprocal is called on, and looking at Demand_ctor I see this:
>>
>> std::fill_n(unit->m_prevout, unit->mNumOutputs, 0.f);
>>
>> This may be an example of why this problem can't be fixed in the general case, because unless I'm missing something, Demand has no way of knowing at construction time what its first output value will be. Zero is the obvious placeholder in that situation.
>
> If Impulse's pre-sample is 1, then Demand's pre-sample could come from
> the demand UGens and not be just 0. (Maybe it wouldn't currently, but
> that could be changed... provided that Impulse triggers the
> calculation.)
>
> hjh
>
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