Re: [Sc-devel] [RFC] sample accurate scheduling

[Sciss <contact@xxxxxxxx>]

maybe you mean a kind of PLL (phase-locked loop) or servo-controlled- 
clock on the sclang side? so it queries in intervals the current  
scsynth clock and adjusts itself accordingly, so that s.latency for  
#sbundle's stay in a safe range?

Am 29.11.2007 um 00:43 schrieb Sciss:

> sounds interesting, but (maybe it's too late in the night) i don't  
> yet get how the #sbundle approach is working.
>
> Am 29.11.2007 um 00:32 schrieb blackrain:
> [...]
> > All that is needed like Jan states, is a one sample impulse and a
> > responder to tell where the synth is.
>
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